Chip Manufacturing Constraints as a Structural Barrier to Orbital Compute

Does the global chip manufacturing bottleneck — ASML EUV tool production, fab capacity, memory supply, and chip allocation dynamics — represent an independent structural argument against orbital compute, beyond the cost premium analyzed in our main TCO model?

Answer

Yes, chip manufacturing constraints are a distinct structural barrier that compounds the cost disadvantage, but they are temporary and unevenly distributed across orbital operators.

The core argument (Patel/SemiAnalysis): in a chip-constrained world, the scarce resource is silicon, not energy. Orbital compute's primary value proposition — free solar power — addresses a factor that is only 5-15% of AI data center TCO, while chips and maintenance represent the remaining 85-95%. Every chip deployed in orbit instead of a terrestrial facility faces the same manufacturing bottleneck but adds 3-6 months of deployment delay (ground testing, launch, commissioning), consuming ~5-10% of useful GPU life in a world where time-to-tokens is the critical metric.

However, this argument applies unevenly:

1. Operators using COTS (commercial off-the-shelf) NVIDIA GPUs (Starcloud, Kepler) face the full force of the allocation constraint. They compete with hyperscalers for the same chips, sit at tier 3-4 of a 4-tier allocation hierarchy, and add orbital deployment delay on top of procurement delay.

2. Operators with custom silicon (Google/Suncatcher with TPUs, SpaceX with D3) partially bypass NVIDIA's allocation hierarchy but still compete for TSMC/Samsung fab capacity and ASML EUV tools — the upstream bottleneck.

3. SpaceX's Terafab is the only proposal that attempts to break the upstream constraint entirely, but its earliest volume production is ~2031 (5 years from groundbreaking per Musk's own estimate), and its 1 TW target implies building capacity comparable to the entire current global AI chip supply chain.

The constraint is structural through ~2030 but likely eases by ~2035 as fab capacity catches up with demand. This timeline aligns with our main analysis: orbital compute does not reach cost parity with terrestrial in any scenario through 2035 (the furthest horizon modeled), so the chip constraint reinforces rather than independently determines the conclusion.

The chip constraint does not change our per-unit economics — orbital and terrestrial operators pay the same chip prices — but it adds three independent penalties: deployment delay (time value of idle chips), procurement risk (allocation uncertainty for non-hyperscaler buyers), and opportunity cost (chips in orbit cannot be easily redeployed if demand patterns shift).

Analysis

The Supply Chain Funnel: A Cascade of Bottlenecks

AI chip production is constrained by a cascading series of bottlenecks, each of which has been the binding constraint at different points:

As of March 2026, the binding constraint has shifted from datacenter power to silicon supply. SemiAnalysis reports that "power is no longer the binding constraint; accelerator silicon supply is" semianalysis-silicon-shortage.4. TSMC reports demand for advanced-node wafers is "about three times" available capacity tsmc-demand-gap.1. Even well-funded AI companies are compute-constrained: Anthropic added $6B ARR in February 2026 alone but was limited by available compute semianalysis-silicon-shortage.8.

A note on the tension between SemiAnalysis and Epoch AI: Epoch AI's 2024 analysis concluded that power and chip availability are both binding constraints, but that power "may be more malleable" since the energy industry is less concentrated epoch-scaling-2030.1. SemiAnalysis's March 2026 analysis reaches a stronger conclusion: silicon supply is now the dominant bottleneck, with power no longer binding. The likely resolution is timeframe: at the time of Epoch's analysis, AI consumed only 12% of advanced logic capacity epoch-packaging-bottleneck.1; by early 2026, AI's share of N3 had risen to 60% (projected 86% by 2027) semianalysis-silicon-shortage.2, fundamentally changing which resource binds first. We weight the SemiAnalysis 2026 analysis more heavily as it reflects current conditions.

The EUV Ceiling

ASML's EUV lithography tools are the ultimate upstream constraint. Every advanced AI chip (sub-7nm) requires EUV patterning, and ASML is the sole manufacturer of EUV lithography systems globally.

Production rates:

• 48 EUV systems shipped in 2025 luminix-euv.1
• 64-67 projected for 2026 (analyst consensus: Kuo 67, BofA 64) luminix-euv.1
• 80-85 projected for 2027 luminix-euv.1
• "A little bit over a hundred by the end of the decade" even under aggressive expansion patel-2024-ai-bottlenecks.1

Why scaling is physically constrained: Each EUV tool contains four major subsystems — EUV source (Cymer/San Diego), reticle stage (Wilmington, CT), wafer stage (Europe), and optics (Carl Zeiss SMT) — with over 10,000 suppliers in the chain [patel-2024-ai-bottlenecks.6, patel-2024-ai-bottlenecks.8]. The bottleneck's bottleneck is Carl Zeiss SMT: Patel estimates probably fewer than 1,000 people work on EUV optics patel-2024-ai-bottlenecks.7, with component positioning accuracy at sub-nanometer levels patel-2024-ai-bottlenecks.8. Zeiss has not aggressively expanded production, and the semiconductor supply chain's conservative investment culture (shaped by historic boom-bust cycles) resists rapid scaling patel-2024-ai-bottlenecks.18.

Tools per GW of AI compute: Approximately 3.5 EUV tools are needed per GW of AI data center capacity at the Rubin generation. The derivation: 1 GW requires ~55,000 wafers of 3nm (20 EUV passes each), ~6,000 wafers of 5nm, and ~170,000 wafers of DRAM, totaling ~2 million EUV wafer passes. Each tool processes ~590,000 passes/year (at ~75 effective wafers/hour accounting for multiple EUV exposures per wafer on advanced nodes, with ~90% uptime) [patel-2024-ai-bottlenecks.3, patel-2024-ai-bottlenecks.4]. (Note: ASML's headline throughput of 220-330 wafers/hour refers to raw exposure throughput; the ~75 wph figure reflects net wafer completions on N3 which requires multiple EUV patterning passes.)

The 200 GW figure and its caveats: Patel calculates ~700 cumulative EUV tools by end of decade (installed base + new production), yielding ~200 GW of theoretical chip capacity at 3.5 tools/GW patel-2024-ai-bottlenecks.13. However, this assumes 100% of EUV capacity goes to AI chips, which is unrealistic — AI consumed only 12% of advanced logic in 2025 epoch-packaging-bottleneck.1, rising to 60% of N3 in 2026 and 86% by 2027 semianalysis-silicon-shortage.2. Realistic AI-dedicated capacity is substantially lower, perhaps 60-150 GW depending on how aggressively AI displaces other workloads. The range is wide enough that the 200 GW figure should be treated as a theoretical ceiling, not a forecast.

Partial offsets: ASML plans to increase EUV source power from 600W to 1kW by ~2030, boosting throughput from 220 to 330 wafers/hour (50% increase), deployable as upgrade packages on existing tools asml-1kw-source.1. However, more EUV-intensive future nodes (N2, A16) require more passes per wafer, partially offsetting the throughput gain.

Who Gets the Chips: Allocation Dynamics

AI accelerator allocation follows a clear hierarchy uvation-h100-availability.1:

1. Sovereign/strategic buyers — governments securing large allocations (Saudi Arabia's Humain received 18,000 AI GPUs from NVIDIA, announced at Saudi-US Investment Forum saudi-gpu-deal.1)
2. Hyperscalers with secured inventory — Microsoft (1.8M+ GPUs), Meta (~600K), with multi-year supply agreements
3. NVIDIA partners/neoclouds — CoreWeave received preferential allocation via NVIDIA's $250M investment, first to deploy GB200 NVL72 and GB300 coreweave-nvidia.1
4. Enterprise and startups — 6-12 month wait times, exorbitant pricing

NVIDIA's structural dominance reinforces this hierarchy: 87% peak AI accelerator market share by revenue in 2024, declining to ~75% by 2026 as AMD and custom silicon scale silicon-analysts-share.1; ~60% of TSMC CoWoS packaging capacity locked up (vs AMD at ~11%) semianalysis-silicon-shortage.6; and $95.2B in forward supply commitments nvidia-q4-fy2026.3.

What this means for orbital operators: A pure-play orbital compute company using commercial NVIDIA GPUs sits at tier 3-4 of this hierarchy. Procurement lead times of 6-12 months, combined with 3-6 months of orbital deployment, mean 9-18 months from order to first revenue — in a world where Patel argues "all that matters is get these chips working on producing tokens ASAP" patel-2024-ai-bottlenecks.14.

Alternatives exist but have limits:

• AMD signed an up-to-6-GW multi-year deal with OpenAI amd-openai-deal.1 and a similar deal with Meta, but has only ~11% of CoWoS capacity and still relies on TSMC
• Secondary markets function: H100s available at 50-85% of new pricing, 300+ GPU cloud providers entered in 2025, hyperscaler on-demand cloud rental down 44% from 2024 introl-secondary-market.1
• Google TPU leasing to third parties is emerging (Meta signed a multibillion-dollar TPU rental deal in February 2026 google-meta-tpu.1)

The Patel Structural Argument

Dylan Patel (SemiAnalysis) presents the most comprehensive skeptical case against orbital compute this decade, resting on three pillars:

Pillar 1: Chips, not power, are the bottleneck. "Space data centers effectively are not limited by their energy advantage. They are limited by the same contended resource. We can only make 200 gigawatts of chips a year by the end of the decade" patel-2024-ai-bottlenecks.13. Energy is only 5-15% of AI data center TCO; chips and maintenance are the rest catalyst-scaling-pathways.2. In a chip-constrained world, the energy advantage is marginal.

Pillar 2: Deployment speed is the critical metric. "All that matters in a chip-constrained world is get these chips working on producing tokens ASAP" patel-2024-ai-bottlenecks.14. Terrestrial data centers go from chip-off-the-line to producing tokens in weeks. Orbital deployment adds 3-6+ months of testing, deconstruction, launch, and commissioning patel-2024-ai-bottlenecks.21. Every day a chip sits idle is wasted value — "10% of your cluster's useful life" for a 6-month delay on a 5-year GPU life.

Pillar 3: Terrestrial can handle rising power density. Higher chip power density requires more exotic cooling. Patel argues: "In space, higher watts per millimeter is very difficult, whereas on Earth these are solved problems" patel-2024-ai-bottlenecks.22.

Corroborating voices: Catalyst podcast analysts reach similar conclusions: "We probably end up bottlenecked by chips before we're really in a world where we can't build everything on the ground" catalyst-scaling-pathways.1.

Assessment: Patel's argument is strong for the 2026-2030 window. His deployment-delay point is the most potent: in a chip-constrained world where compute is most valuable in its first months, any additional latency to first revenue is a real economic penalty. However, the argument has a built-in expiration date — it applies only while chips remain the binding constraint. Patel himself estimates this eases by ~2035 patel-2024-ai-bottlenecks.15.

Orbital Chip Strategies: Can Operators Route Around the Bottleneck?

Three procurement strategies are visible across the orbital compute industry:

Track 1: Commercial NVIDIA GPUs. Starcloud placed the first H100 in space (November 2025, 60 kg satellite starcloud-nvidia.1). Kepler launched 10 satellites with multi-GPU modules (January 2026 introl-2026.1). NVIDIA's Space-1 Vera Rubin Module (announced GTC 2026) offers 25x H100 performance purpose-built for space, with six launch customers payload-nvidia-space1.1. This track faces the full allocation constraint — operators compete directly with hyperscalers for the same chips.

Track 2: Custom silicon bypassing NVIDIA. Google's Suncatcher uses Trillium TPU v6e chips, radiation-tested to 3x the shielded 5-year mission dose google-suncatcher.1. SpaceX announced the D3 chip at its March 2026 Terafab presentation — designed to run hotter than terrestrial chips with radiation protection, to be manufactured at the planned Terafab spacex-ai-sat-mini-spacenews.1. Custom silicon sidesteps NVIDIA's allocation hierarchy but still competes for TSMC/Samsung fab capacity — the upstream bottleneck persists.

Track 3: Custom fabs (Terafab). SpaceX/xAI's Terafab is the only proposal that attempts to break the upstream constraint entirely. Targets ~1M wafers/month covering logic, memory, and packaging, claiming 1 TW annual processor production — "50 times the combined production rate of all manufacturers of chips used today in advanced applications" spacex-ai-sat-mini-spacenews.2. Musk investing up to $25B spacex-ai-sat-mini-daniel-marin.1. However, Musk's own estimate is 5 years from groundbreaking to volume production musk-2026.2, placing earliest output at ~2031. The 1 TW target implies building capacity comparable to the entire global semiconductor supply chain — an extraordinary claim.

The memory problem: Musk identifies memory as potentially harder than logic: "I think the path to creating logic chips is more obvious than the path to having sufficient memory" musk-2026.5. HBM faces a supply shortfall of ~5-9% persisting through 2027, with the wafer deficit exceeding 20% [semianalysis-memory-mania.1, sk-hynix-shortage.1]. Three companies (SK Hynix, Samsung, Micron) control 97% of HBM production hbm-export-controls.1. Custom fabs do not solve memory supply unless they also build memory production lines.

Is This Independent of the Cost Argument?

Our main TCO model already captures chip cost as the dominant component of both orbital and terrestrial systems (GPU cost per kW_IT is the single largest line item). The chip manufacturing constraint adds three penalties not captured in the per-unit cost model:

1. Time value of idle chips. A chip waiting 3-6 months for orbital deployment instead of producing revenue from a terrestrial rack has an opportunity cost. At $1.40/hour H100 TCO and ~5-year useful life, 6 months of idle time costs ~$6,100 per GPU — a ~10% lifecycle penalty that increases as chip scarcity drives up the marginal value of compute.

2. Procurement risk. An orbital operator without hyperscaler-tier purchasing power faces allocation uncertainty that terrestrial operators with established supplier relationships do not. This is a real but diminishing barrier — NVIDIA's Space-1 module and the secondary market both provide alternative procurement channels.

3. Irreversibility of deployment. Chips launched to orbit cannot be redeployed to terrestrial facilities if demand patterns shift or newer, more efficient chips become available. Terrestrial operators can sell or reallocate hardware; orbital operators cannot. In a rapidly evolving chip landscape with 2-year generational cadences, this inflexibility is a distinct risk.

Timeline: When Does the Constraint Ease?

The chip manufacturing bottleneck is structural through ~2030 but not permanent:

• Memory relief: SK Group chairman projects wafer shortage through 2030, with deficit >20% requiring 4-5 years of capacity building sk-hynix-shortage.1
• Logic capacity: TSMC cannot add enough N3/N2 capacity for the next 2 years (through 2028) semianalysis-silicon-shortage.1
• EUV tools: ~100/year by 2030, with semiconductor supply chain "not AI pilled" patel-2024-ai-bottlenecks.18
• ASML throughput: 50% improvement by ~2030 via 1kW source upgrade asml-1kw-source.1
• Patel's estimate: Semiconductor industry catches up with demand by ~2035 patel-2024-ai-bottlenecks.15

This timeline aligns with our main analysis: orbital compute does not reach cost parity with terrestrial in any scenario through 2035. The chip constraint reinforces the cost conclusion through an independent mechanism — orbital compute faces both a persistent cost premium AND a chip procurement disadvantage during the 2026-2032 window.

Post-2035, the argument inverts: if chip supply catches up with demand and energy becomes a larger share of TCO, orbital compute's free-solar advantage gains relative importance. This is precisely when our model shows the orbital cost curve approaching (though not reaching) terrestrial TCO.

Implications for the Main Analysis

The chip manufacturing constraint does not change our model's per-unit economics (same chips, same price regardless of deployment location). It does affect the practical viability timeline through three mechanisms:

1. Deployment delay penalty — now captured via the effective lifetime model, which reduces the productive operating window T by deployment delay (see orbital-operational-lifetime page). At $1.40/hour H100 TCO and ~5-year useful life, 6 months of idle time costs ~$6,100 per GPU — a ~10% lifecycle penalty that increases as chip scarcity drives up the marginal value of compute.

2. Scale-up constraint — orbital compute cannot scale faster than its chip procurement allows. Operators using COTS GPUs are constrained by the same allocation hierarchy as any tier 3-4 buyer. Operators with custom silicon (Google, SpaceX) can potentially secure dedicated fab capacity but still face EUV tool and memory constraints.

3. The "additive demand" problem — orbital compute does not create new chip supply; it adds demand to an already-constrained market. Unless Terafab (or equivalent) materializes, every GPU launched to orbit is one fewer GPU available for terrestrial deployment. This creates a zero-sum dynamic that favors whoever can deploy chips fastest — currently terrestrial operators by a wide margin.

None of these change the fundamental cost-parity timeline, but they add practical barriers that make the optimistic scenario (orbital parity by ~2033) less likely to be achieved on schedule even if cost projections prove accurate.

Sources

semianalysis-silicon-shortage

• URL: https://open.substack.com/pub/semianalysis/p/the-great-ai-silicon-shortage
• Title: The Great AI Silicon Shortage
• Description: SemiAnalysis analysis of front-end wafer capacity as the dominant AI compute bottleneck (March 2026)
• Summary: Documents structural shift from power-constrained to silicon-supply-constrained AI compute. NVIDIA locked majority of logic, memory, and component supply. N3 fully utilized through 2027.

semianalysis-memory-mania

• URL: https://reader.secondthoughts.workers.dev/posts/835/view
• Title: Memory Mania: How a Once-in-Four-Decades Shortage Is Fueling a Memory Boom
• Description: SemiAnalysis analysis of HBM capacity dynamics and dual memory shortage
• Summary: HBM wafer capacity 5x-ing in 4 years but supply shortfall persists at 5-9% through 2027. Commodity DRAM also in ~7% deficit.

epoch-packaging-bottleneck

• URL: https://epochai.substack.com/p/advanced-packaging-and-hbm-not-logic
• Title: Advanced packaging and HBM — not logic dies — were the bottlenecks on AI chip production in 2025
• Description: Epoch AI analysis showing AI consumed ~90% of packaging/HBM but only 12% of logic in 2025
• Summary: CoWoS and HBM are almost entirely consumed by AI demand; logic serves broader markets.

epoch-scaling-2030

• URL: https://epoch.ai/blog/can-ai-scaling-continue-through-2030
• Title: Can AI scaling continue through 2030?
• Description: Epoch AI assessment of chip manufacturing vs power as binding constraint
• Summary: Projects ~100M H100-equiv GPUs by 2030. Concludes power binds before chips.

luminix-euv

• URL: (Luminix industry analysis)
• Title: ASML EUV Shipment Projections
• Description: Independent analysis corroborating ASML production rates
• Summary: 48 EUV systems shipped in 2025. Consensus: 64-67 for 2026, 80-85 for 2027.

asml-1kw-source

• URL: https://wccftech.com/asml-set-to-boost-chip-output-by-ramping-euv-power-to-a-kilowatt/
• Title: ASML Set to Boost Chip Output 50% by 2030
• Description: ASML 1kW EUV source upgrade to boost throughput 50%
• Summary: Source power from 600W to 1kW enables 330 wph (from 220). Upgrade packages for existing tools.

tsmc-demand-gap

• URL: (TSMC earnings, TrendForce, Fusion Worldwide)
• Title: TSMC Advanced Node Demand Gap
• Description: TSMC reports demand 3x available advanced-node capacity
• Summary: Demand "about three times" available capacity; suppliers could sell "20-50% more" if it existed.

nvidia-q4-fy2026

• URL: https://fortune.com/2026/02/25/nvidia-nvda-earnings-q4-results-jensen-huang/
• Title: Nvidia FY2026 Q4 results — $68B revenue
• Description: NVIDIA financial results showing $216B annual revenue and $95B supply commitments
• Summary: FY2026 data center revenue $197.3B. Supply commitments nearly doubled to $95.2B.

uvation-h100-availability

• URL: https://uvation.com/articles/h100-availability-the-silent-crisis-threatening-enterprise-ai-plans
• Title: H100 Availability: The Silent Crisis
• Description: Analysis of 4-tier GPU allocation hierarchy and enterprise access barriers
• Summary: Enterprises face 6-12 month waits. Grey market at $25-40/hour.

coreweave-nvidia

• URL: https://introl.com/blog/coreweave-gpu-cloud-ai-infrastructure-deep-dive-2025
• Title: CoreWeave Deep Dive
• Description: CoreWeave's preferential NVIDIA allocation via $250M investment
• Summary: First to deploy GB200 NVL72 and GB300. Fleet: 250K+ GPUs.

silicon-analysts-share

• URL: https://siliconanalysts.com/analysis/nvidia-ai-accelerator-market-share-2024-2026
• Title: NVIDIA GPU Market Share 2024-2026
• Description: NVIDIA market dominance and competitive dynamics
• Summary: 87% peak share (2024), declining to ~75% (2026). H100: $3,320 cost, $28,000 price.

saudi-gpu-deal

• URL: https://www.tomshardware.com/pc-components/gpus/nvidia-sending-18-000-ai-gpus-to-saudi-arabias-state-backed-ai-data-centers-in-wake-of-cancelled-export-rules
• Title: NVIDIA sending 18,000 GPUs to Saudi Arabia
• Description: NVIDIA GPU shipment to Saudi Arabia following US export rule cancellation
• Summary: 18,000 AI GPUs shipped to Saudi Arabia's Humain for 500MW datacenter.

amd-openai-deal

• URL: https://logisticsviewpoints.com/2025/10/06/amd-and-openai-sign-long-term-gpu-deployment-agreement-strategic-and-supply-chain-considerations/
• Title: AMD-OpenAI 6 GW multi-year GPU deal
• Description: AMD deploys Instinct GPUs to OpenAI with equity component
• Summary: 6 GW MI450 starting H2 2026. AMD issued ~10% equity warrant.

introl-secondary-market

• URL: https://introl.com/blog/secondary-gpu-markets-buying-selling-used-hardware-guide-2025
• Title: Secondary GPU Markets Guide 2025
• Description: Secondary GPU market pricing and structure
• Summary: H100 at 50-85% of new. 300+ new GPU cloud providers in 2025.

google-meta-tpu

• URL: https://reader.secondthoughts.workers.dev/posts/1482/view
• Title: Google-Meta Multibillion-Dollar TPU Rental Deal
• Description: Meta signs multi-year TPU deal with Google
• Summary: Signals chip supply constraints driving diversification among largest buyers.

sk-hynix-shortage

• URL: https://www.networkworld.com/article/4146270/chip-wafer-shortage-will-run-through-2030-as-ai-demand-overwhelms-supply-sk-hynix-chief.html
• Title: Chip wafer shortage through 2030 — SK Hynix chief
• Description: SK Group chairman projects wafer shortage through 2030
• Summary: Wafer deficit >20%, requiring 4-5 years of capacity building.

hbm-export-controls

• URL: https://reader.secondthoughts.workers.dev/posts/712/view
• Title: High-Bandwidth Memory: Critical Gaps in Export Controls
• Description: HBM industry concentration — 3 companies control 97% of production
• Summary: SK Hynix (53-62%), Samsung (35%), Micron (11%).

catalyst-scaling-pathways

• URL: https://traffic.megaphone.fm/PSMI5018200682.mp3
• Title: AI scaling pathways: on grid, on edge, off grid, off planet
• Description: Latitude Media / Catalyst podcast on compute scaling bottlenecks
• Summary: Chip supply binds before energy. Energy is 5-15% of AI DC cost.

spacex-ai-sat-mini-spacenews

• URL: https://spacenews.com/spacex-offers-details-on-orbital-data-center-satellites/
• Title: SpaceX offers details on orbital data center satellites
• Description: SpaceX D3 chip and Terafab announcement (March 2026)
• Summary: D3 chip runs hotter with radiation protection. Terafab targets 1 TW annual production.

spacex-ai-sat-mini-daniel-marin

• URL: https://danielmarin.naukas.com/2026/03/23/ai-sat-mini-los-centros-de-datos-orbitales-de-spacex-de-180-metros-de-longitud/
• Title: AI Sat Mini technical analysis
• Description: Analysis of AI Sat Mini from Terafab presentation
• Summary: Musk investing up to $25B in Terafab. AI Sat Mini ~180m, 100 kW, ~1 ton.

musk-2026

• URL: https://www.dwarkesh.com/p/elon-musk
• Title: Elon Musk — "In 36 months, the cheapest place to put AI will be space"
• Description: Musk on Terafab, chip supply, and orbital compute timeline
• Summary: Booked all available fab capacity. Terafab ~1M wpm. Memory is "biggest concern."

starcloud-nvidia

• URL: (CNBC, December 2025)
• Title: Starcloud Places First NVIDIA H100 GPU in Space
• Description: First H100 in orbit (early November 2025)
• Summary: 60 kg Starcloud-1 satellite. 100x more compute than previously in orbit.

payload-nvidia-space1

• URL: (Payload newsletter, March 2026)
• Title: Nvidia Unveils Space-1 Vera Rubin Module
• Description: NVIDIA purpose-built space compute at GTC 2026
• Summary: 25x H100 compute. Six launch customers.

google-suncatcher

• URL: (Google Research blog)
• Title: Google Project Suncatcher TPU radiation testing
• Description: Trillium TPU v6e radiation test results
• Summary: HBM irregularities after 2 krad(Si). No hard failures to 15 krad(Si).

introl-2026

• URL: (Introl, 2026)
• Title: Orbital Data Center Competitive Landscape 2026
• Description: Mapping of orbital operators to chip procurement strategies
• Summary: Operators split across commercial NVIDIA, custom silicon, and custom fab strategies.

Evidence

1. ASML produces about 70 EUV tools per year (2026), targeting ~80 next year, "a little bit over a hundred by the end of the decade" even under aggressive expansion. — patel-2024-ai-bottlenecks

2. ~3.5 EUV tools required per GW of AI data center capacity (Rubin generation): 1 GW needs ~2 million EUV wafer passes. — patel-2024-ai-bottlenecks

3. A 1 GW AI data center requires ~55,000 wafers of 3nm (20 EUV passes each), plus ~6,000 wafers of 5nm, plus ~170,000 wafers of DRAM memory. — patel-2024-ai-bottlenecks

4. Each EUV tool has four subsystems: EUV source (Cymer, San Diego), reticle stage (Wilmington, CT), wafer stage (Europe), optics (Carl Zeiss SMT). Over 10,000 suppliers in the chain. — patel-2024-ai-bottlenecks

5. Carl Zeiss SMT: "probably employs like less than a thousand people working on this." Zeiss market cap ~$2.5B. — patel-2024-ai-bottlenecks

6. ASML's supply chain has over 10,000 suppliers. Layer-to-layer overlay accuracy must be ~3 nanometers; component positioning accuracy sub-1 nanometer. — patel-2024-ai-bottlenecks

7. ASML shipped 48 EUV systems in 2025. Analyst consensus: 64-67 for 2026 (Kuo: 67; BofA: 64), 80-85 for 2027. ASML targeting 50% throughput gain to 330 wafers/hour by 2030. — luminix-euv

8. ASML plans to increase EUV source power from 600W to 1kW by ~2030, boosting throughput from 220 to 330 wafers/hour (50% increase), deployable as upgrade packages on existing tools. — asml-1kw-source

9. The four largest AI chip designers consumed ~90% of global advanced packaging and HBM in 2025, while AI chips took only 12% of advanced logic capacity. — epoch-packaging-bottleneck

10. TSMC N3 capacity: ~200K wpm (2026), ~250K wpm (2027). Effective utilization expected to exceed 100% in H2 2026. TSMC cannot add enough capacity for the next 2 years. — semianalysis-silicon-shortage

11. AI demand takes ~60% of TSMC N3 output in 2026, rising to 86% by 2027 — nearly entirely squeezing out smartphone and CPU wafers. — semianalysis-silicon-shortage

12. "Power is no longer the binding constraint; accelerator silicon supply is." Front-end logic wafer capacity is now the dominant bottleneck, with CoWoS easing. — semianalysis-silicon-shortage

13. NVIDIA controls ~60% of TSMC's CoWoS advanced packaging capacity; AMD has only ~11%. — semianalysis-silicon-shortage

14. Anthropic added $6B ARR in February 2026 alone and would have added more if not compute-constrained. — semianalysis-silicon-shortage

15. TSMC reports demand for advanced-node wafers is "about three times" available capacity. Suppliers could sell "20-50% more" if capacity existed. — tsmc-demand-gap

16. HBM wafer capacity 5x-ing in 4 years. HBM share of DRAM wafers: 5% (2022) to 20% (2025) to 35% (2027). Supply shortfall: ~5% (2025), ~6% (2026), ~9% (2027). — semianalysis-memory-mania

17. SK Group Chairman Chey Tae-won: industry faces wafer deficit of more than 20%, requiring at least 4-5 years of capacity building. "The current shortage could continue until 2030." — sk-hynix-shortage

18. Three companies (SK Hynix, Samsung, Micron) control 97% of HBM wafer production. — hbm-export-controls

19. NVIDIA supply commitments: $95.2B at end Q4 FY2026, nearly doubled from $50.3B at end Q3. — nvidia-q4-fy2026

20. NVIDIA has locked in majority of supply for logic wafers, memory, and components through proactive procurement. — semianalysis-silicon-shortage

21. 4-tier GPU allocation hierarchy: (1) sovereign/strategic, (2) hyperscalers, (3) NVIDIA partners, (4) enterprise/startups facing 6-12 month wait times. — uvation-h100-availability

22. NVIDIA invested $250M in CoreWeave, provided preferential allocation. CoreWeave first to deploy GB200 NVL72 (Feb 2025) and GB300 (Jul 2025). Fleet: 250K+ GPUs. — coreweave-nvidia

23. NVIDIA: 87% peak AI accelerator market share (2024), declining to ~75% by 2026. H100 cost ~$3,320, sells ~$28,000 (88% gross margin). Competitive floor ~65-70% due to CUDA lock-in. — silicon-analysts-share

24. NVIDIA announced shipment of 18,000 AI GPUs to Saudi Arabia's Humain, following US cancellation of pending AI diffusion export rules that would have complicated such transactions. — saudi-gpu-deal

25. AMD signed up to 6 GW multi-year deal with OpenAI (MI450, starting H2 2026). AMD issued warrant for up to 160M shares (~10% stake). — amd-openai-deal

26. H100 secondary pricing: 70-85% of new (1-2 years), 50-70% (2-3 years). 300+ new GPU cloud providers entered 2025. Hyperscaler on-demand cloud rental down 44% from 2024. — introl-secondary-market

27. Meta signed multi-year, multibillion-dollar deal to rent Google's TPUs for AI model development (February 2026). — google-meta-tpu

28. SpaceX D3 chip: "optimized for use in space, designed to run hotter than terrestrial chips and with radiation protection," to be manufactured at Terafab. — spacex-ai-sat-mini-spacenews

29. Terafab targets 1 TW annual processor production — "50 times the combined production rate of all manufacturers of chips used today in advanced applications." — spacex-ai-sat-mini-spacenews

30. Musk investing up to $25B in Terafab for xAI/Tesla/SpaceX chip supply. — spacex-ai-sat-mini-daniel-marin

31. Musk has booked all available TSMC Taiwan, Samsung Korea, TSMC Arizona, Samsung Texas capacity. Five-year timeline from groundbreaking to volume production for new fabs. — musk-2026

32. Musk on memory: "I think the path to creating logic chips is more obvious than the path to having sufficient memory... That's why you see DDR prices going ballistic." — musk-2026

33. Google tested Trillium TPU v6e in 67MeV proton beam. HBM irregularities after 2 krad(Si) — nearly 3x the expected shielded 5-year dose. No hard TID failures up to 15 krad(Si). — google-suncatcher

34. First NVIDIA H100 in space: early November 2025, aboard 60 kg Starcloud-1 satellite. "100x more powerful GPU compute than any previous space-based operation." — starcloud-nvidia

35. NVIDIA Space-1 Vera Rubin Module at GTC 2026: up to 25x H100 compute, purpose-built for space. Six launch customers announced. — payload-nvidia-space1

36. Epoch AI projects ~100M H100-equiv GPUs by 2030 (range 20M-400M). Concludes "the most binding constraints are power and chip availability," with power being "may be more malleable" since the energy industry is less concentrated. — epoch-scaling-2030

37. "Space data centers effectively are not limited by their energy advantage. They are limited by the same contended resource. We can only make 200 gigawatts of chips a year by the end of the decade." — patel-2024-ai-bottlenecks

38. "All that matters in a chip-constrained world is get these chips working on producing tokens ASAP... There are things people are doing to decrease that time that you cannot do in space." — patel-2024-ai-bottlenecks

39. "At some point, we do cross the chasm where space data centers make sense, but it's not this decade... once chips are no longer the bottleneck." Maybe by 2035. — patel-2024-ai-bottlenecks

40. "There's no way to just snap your fingers and increase production." The semiconductor supply chain is "not AI pilled." — patel-2024-ai-bottlenecks

41. On orbital deployment delay: "I don't see how you would test them all on Earth, deconstruct them and ship them into space and it not take longer than just putting them in the spot that you were testing them." — patel-2024-ai-bottlenecks

42. Higher chip power density "requires much more exotic cooling. In space, higher watts per millimeter is very difficult, whereas on Earth these are solved problems." — patel-2024-ai-bottlenecks

43. "We probably end up bottlenecked by chips before we're really in a world where we can't build everything on the ground." — catalyst-scaling-pathways

44. "Energy is only 5 to 15% of an AI-focused data center and chips and maintenance are the rest. And you're stuck with the same chip cost whether you put the thing in space or on Earth." — catalyst-scaling-pathways

45. Kepler Communications launched 10 satellites with multi-GPU compute modules in January 2026, using commercial NVIDIA hardware in orbit. — introl-2026